Calibre
Calibre SVRF TVF Rule Decks Guide
Comprehensive guide to Siemens Calibre SVRF and TVF rule decks for physical verification. Learn rule syntax, DRC/LVS deck structure, PERC, and debug best practices.
SkyCadEda Engineering·
Introduction to Calibre SVRF and TVF Rule Decks
Calibre is Siemens EDA's industry-leading physical verification platform, used by virtually every semiconductor foundry and design house for Design Rule Checking, Layout vs Schematic comparison, and reliability verification. At the heart of every Calibre verification run lies a rule deck written in one of two languages: SVRF, the Standard Verification Rule Format, or TVF, the Tcl Verification Format. SVRF is the traditional, declarative rule language that has been the backbone of Calibre verification for decades. TVF is a newer, Tcl-based alternative that offers procedural programming constructs, dynamic variable scoping, and easier integration with external data sources. Understanding both formats is essential for any physical verification engineer working at advanced process nodes.SVRF: The Standard Verification Rule Format
SVRF is a declarative, rule-based language specifically designed for physical verification. A typical SVRF rule deck consists of layer definitions, derived layer operations, DRC checks, and output statements. Layer definitions map GDSII layer numbers to logical names using the LAYER statement. Derived layers are created through boolean and geometric operations, including AND, OR, NOT, XOR, SIZE, GROW, SHRINK, and DRC CHECK operations that test specific design constraints. SVRF uses a non-procedural evaluation model where the order of statements does not affect the logical result, though it can affect performance. The language supports variables, arithmetic expressions, and conditional execution through IF-ELSE constructs, but it remains fundamentally a rule-description language rather than a general-purpose programming language.TVF: Tcl Verification Format for Procedural Control
TVF extends Calibre with full Tcl programming capabilities, allowing rule deck developers to use loops, procedures, file I/O, regular expressions, and dynamic data structures. A TVF rule deck uses standard Tcl syntax: variables set with the set command, procedures defined with proc, conditional logic with if and switch, and looping with for and foreach constructs. TVF also provides Calibre-specific commands that mirror SVRF operations, such as drc, lvs, and extract commands, while adding the flexibility of Tcl's string manipulation and math expression capabilities. TVF is particularly valuable for advanced-node rule decks that require complex rule generation based on parametric inputs, process corner data, or look-up tables. Many foundries now provide hybrid rule decks that use TVF for procedural logic while calling SVRF-style rule blocks for the actual verification operations.DRC Rule Deck Structure and Organization
A production DRC rule deck is organized into distinct functional sections for maintainability and performance. The preamble section defines technology constants, layer definitions, and global variables. The derived-layer computation section creates all intermediate layers needed for checks, such as pin-to-pin spacing layers, density calculation layers, and antenna diode layers. The main DRC check section contains individual rule checks organized by category: spacing, width, enclosure, density, antenna, and pattern-matching checks. Each check typically includes a rule statement, an error description, and severity level. The output section configures how results are reported, including RVE-compatible database output for Siemens Calibre RVE, text reports, and hierarchical result databases. Advanced rule decks also include per-cell or per-block rule parameters for mixed-signal and multi-voltage designs.Common DRC Checks in SVRF and TVF
The most common DRC checks are implemented using straightforward geometric operations. A minimum spacing check creates a sized version of the layer being checked and looks for overlaps with the original. A minimum width check erodes then grows the layer by half the minimum width; any remaining geometry fails. An enclosure check, such as via enclosure by metal, creates a sized version of the enclosing layer and checks that it fully covers the inner layer. Density checks compute the fraction of area occupied by a layer within a sliding window and compare against minimum and maximum density targets. Antenna checks measure the ratio of gate oxide area to connected metal area to ensure plasma-induced damage during fabrication stays within limits. All of these checks can be expressed equivalently in SVRF or TVF, though TVF offers advantages for parameterized rules.LVS Rule Deck Structure and Connectivity Extraction
LVS rule decks define how the Calibre tool extracts the connectivity graph from the layout and compares it against the schematic netlist. The extraction begins with device recognition, where specific layer combinations and geometries identify transistors, resistors, capacitors, and diodes. The LVS deck defines gate, source, drain, and bulk terminals for each device type using layer operations and connectivity tracing. The interconnect extraction uses layer-to-layer contact definitions and via recognition to build the complete netlist with parasitic resistance and capacitance. The comparison step maps layout nodes to schematic nodes and reports mismatches, shorts, opens, and parameter mismatches. Advanced LVS decks handle multiple threshold voltage variants, analog matching structures, and electro-static discharge protection devices with specialized recognition rules.PERC Reliability Rule Decks
Calibre PERC extends physical verification beyond traditional DRC and LVS by checking circuit reliability constraints through electrical rule checking. PERC rule decks analyze the connectivity graph to identify potential reliability issues such as electro-migration hotspots, voltage stress on thin-oxide devices, ESD protection network continuity, and power domain crossings. A PERC rule deck combines device recognition, connectivity tracing through the extracted netlist, and conditional checks that flag violations based on path properties. For example, a PERC rule can trace all current paths from a high-voltage pad to low-voltage core logic and verify that appropriate level-shifter cells and voltage clamp diodes are present at each interface. PERC decks are typically written in TVF because they require procedural graph traversal and complex conditional logic that is difficult to express in SVRF.Rule Deck Debugging and Optimization
Debugging Calibre rule decks requires systematic analysis of verification results and performance data. The Calibre RVE debugger provides interactive visualization of DRC violations with cross-probing between error markers and the layout database. For performance optimization, rule deck developers use Calibre's built-in profiling tools that report rule-by-rule execution time and memory usage. Common optimization techniques include: combining multiple spacing checks into a single operation where possible; using layer partitioning to limit check scope; avoiding unnecessary derived layer creation through direct operation chaining; and using the dbLayerAndNot and dbLayerOr commands to minimize intermediate database operations. TVF rule decks offer additional optimization opportunities through procedural flow control, allowing early exit from expensive checks when a design fails critical basic rules first.Integration with the Physical Verification Flow
Calibre rule decks integrate into the broader physical verification flow through command files and run scripts. A typical verification flow consists of: extraction of full-chip or block-level GDSII data; hierarchical DRC with Calibre -drc command, which applies the DRC rule deck; LVS with Calibre -lvs command for connectivity verification; RVE debugging; and optional PERC analysis. The run script, typically written in Tcl or Perl, orchestrates these steps and manages technology files, rule deck versions, and result databases. For hierarchical verification, Calibre supports cell-by-cell checking with results integration, reducing total runtime for large designs. Modern flows also integrate Calibre sign-off into the design closure loop, allowing incremental checking after engineering change orders without a full re-run of the entire deck.Best Practices for Rule Deck Development
Developing production-quality Calibre rule decks requires rigorous methodology. Always version-control rule decks using Git or similar systems, with semantic versioning to track changes. Write detailed comments for each rule explaining its purpose, the design rule manual reference, and any process-dependent assumptions. Use consistent naming conventions: prefix derived layers with a short identifier, name checks by rule number or descriptive tag, and group related checks into named rule blocks. Maintain a regression test suite with known-good and known-bad test layouts to validate changes. Document the minimum, typical, and maximum runtime for each rule group to catch performance regressions. For foundry-delivered rule decks, never modify the original files directly; instead, create a wrapper deck that extends or customizes the base rules for your specific design and technology needs.Future Trends: Machine Learning and Rule Automation
The future of Calibre rule deck development is being shaped by machine learning and automation. Siemens EDA's Calibre ML technology applies machine learning models to predict DRC violations during the routing phase, reducing DRC turnaround time. Rule deck developers are also exploring automated rule generation from foundry design rule manuals using natural language processing, though this remains experimental. At advanced nodes below 5nm, the number of design rules has grown exponentially, with leading-edge rule decks containing thousands of individual checks. This complexity is driving adoption of TVF for its programmatic strengths, enabling rule decks to generate checks dynamically based on context. For SkyCadEda engineers working with Calibre, mastery of both SVRF and TVF rule deck development is a key differentiator in delivering high-quality physical verification services.Related Articles
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Frequently Asked Questions
What is the difference between SVRF and TVF in Calibre?+
SVRF is the Standard Verification Rule Format, a declarative rule language designed specifically for physical verification DRC and LVS rule decks. TVF is the Tcl Verification Format, which extends Calibre with full Tcl scripting capabilities including loops, procedures, file I/O, and dynamic data structures. SVRF is simpler and more widely used for standard rule decks, while TVF is preferred for advanced rule decks requiring complex programmatic logic, parametric rule generation, and integration with external data sources.
How do I debug a Calibre DRC violation?+
Use Calibre RVE, the Results Viewing Environment, to visualize DRC violations with cross-probing between error markers and the layout. RVE shows each violation's coordinates, the layers involved, and the specific rule that was violated. For rule deck debugging, use Calibre's built-in profiling tools to identify slow rules, and systematically test individual rule groups by commenting out sections and checking partial results. Start with basic spacing and width checks before debugging complex density or antenna rules.
What are PERC rules in Calibre?+
PERC rules are circuit reliability checks that go beyond traditional DRC and LVS. They analyze the electrical connectivity graph to detect issues like electro-migration hotspots, voltage stress violations, ESD protection failures, and floating gates. PERC decks are typically written in TVF because they require procedural graph traversal, path analysis, and conditional logic. They are essential for automotive, aerospace, and high-reliability semiconductor designs.
Can I use both SVRF and TVF in the same rule deck?+
Yes, Calibre supports hybrid rule decks that combine SVRF and TVF. You can use TVF for the procedural framework, variable definition, and conditional logic, while calling SVRF-style rule blocks for the actual DRC and LVS checks. This hybrid approach is widely used in advanced-node foundry rule decks, where TVF handles complex rule generation and corner-case handling while SVRF provides a clean, readable syntax for the verification operations themselves.
How do I optimize Calibre rule deck performance?+
Key optimization techniques include: combining multiple spacing checks into a single pass; using direct operation chaining to minimize intermediate layers; partitioning checks by cell hierarchy to limit scope; using the debug_rules and rule_area commands to profile individual rule performance; avoiding redundant operations through conditional execution; and using TVF's procedural flow control to run expensive checks only when necessary. Also ensure that derived layers are ordered efficiently so that each layer is computed exactly once and consumed as early as possible.