Schematic & Netlist Translation
Scheture is SkyCadEda's schematic capture and netlist translation tool for custom IC design. It provides an intuitive schematic entry environment with bi-directional netlist translation between Verilog, CDL (Circuit Design Language), and SPICE formats. Scheture bridges the gap between digital and analog design domains, enabling mixed-signal IC teams to move seamlessly between schematic capture, netlisting, and simulation workflows.
Scheture provides a clean, responsive schematic editor for hierarchical circuit entry. Place symbol instances, draw wires, define bus structures, and annotate design parameters with an interface optimized for analog, mixed-signal, and custom digital IC schematic capture. Full undo/redo, copy/paste, and keyboard shortcuts accelerate schematic editing.
Translate netlists between Verilog, CDL, and SPICE formats with accurate, round-trip netlist conversion. Scheture preserves hierarchy, device parameters, connectivity, and naming conventions across formats, enabling teams to use the same schematic for digital simulation in Verilog and analog simulation in SPICE or CDL.
Auto-generate schematic symbols from netlist data, SPICE subcircuits, or Verilog module definitions. Manage centralized symbol libraries with version tracking, naming conventions, and foundry compatibility checks. Scheture symbol generator reduces manual library maintenance effort for IP-heavy custom IC design projects.
Cross-probe between schematic views and layout databases for interactive debug and verification. Select a device or net in the schematic and highlight the corresponding geometry in Slam-Edit, or vice versa. Cross-probing accelerates LVS debug, layout-vs-schematic review, and design intent verification.
Mixed-signal IC design teams face a unique challenge: the analog and digital design domains use different netlist formats, different simulation tools, and different design methodologies. Scheture bridges this gap by providing a single schematic capture environment that translates seamlessly between Verilog, CDL, and SPICE netlist formats. Engineers capture the circuit once and generate netlists for every downstream tool.
As a schematic editor, Scheture supports hierarchical design entry with nested symbol instances, bus notation, global nets, and design rule annotations. The netlist converter engine handles format-specific nuances — SPICE device models, CDL subcircuit syntax, Verilog port declarations — ensuring that translated netlists are simulation-ready without manual post-processing.
Custom IC projects reuse large numbers of IP blocks — standard cells, analog macros, I/O pads, memory compilers. Scheture symbol generation tool automatically creates schematic symbols from netlist definitions, SPICE subcircuit files, or Verilog module declarations. This eliminates the manual effort of drawing symbols for every IP block and keeps your symbol library synchronized with the actual IP netlist.
Scheture is a core component of the SkyCadEda SLAM product suite. Schematics created in Scheture connect to Slam-Edit for layout implementation and to Slam-View for layout review. Cross-probing between schematic and layout, netlist-driven layout assistance, and unified design data management provide a cohesive custom IC design environment that reduces tool fragmentation and data translation overhead.
Schematic capture is the process of creating a structured circuit representation by placing device symbols and connecting them with wires in a graphical editor. For custom IC design, schematic capture defines the circuit topology, device sizing, and connectivity that drives layout implementation, simulation, and verification. A reliable schematic capture tool is the foundation of every analog, mixed-signal, and custom digital IC design flow.
Scheture supports bi-directional netlist translation between Verilog (including Verilog-A and structural Verilog), CDL (Circuit Design Language used by Cadence and foundry PDKs), and SPICE (including HSPICE, Spectre, and Eldo dialects). Translation preserves hierarchy, device instance parameters, pin ordering, net naming, and subcircuit definitions for accurate cross-format interoperability.
Yes. Scheture translates Verilog netlists to CDL format, mapping module hierarchies to subcircuit definitions, preserving port ordering, and converting parameter syntax. This is essential for mixed-signal teams that design in Verilog but need CDL netlists for Virtuoso simulation or foundry verification. Reverse CDL-to-Verilog translation is also supported.
Yes. Scheture supports cross-probing between schematic and layout views through integration with SkyCadEda's Slam-Edit layout editor. You can select a device or net in the Scheture schematic and highlight the corresponding geometry in the layout, or select layout geometry and navigate to the schematic source. This accelerates LVS debug and layout-vs-schematic verification.