Techfile and Layer Setup
Definition of layers, vias, constraints, display resources, and process rules aligned to foundry documentation. We configure techfiles for Virtuoso, Custom Compiler, and third-party tool environments.
Foundry Kit Enablement
PDK Setup Services for Production-Ready Design Environments
SkyCadEda helps semiconductor teams operationalize process design kits quickly and safely. We handle technology file configuration, CDF behavior, device model alignment, and integration validation so designers can focus on execution instead of environment friction. Our engineers have worked with TSMC, GlobalFoundries, Samsung, and specialty foundry nodes from 180nm down to advanced FinFET processes.
CDF Parameters and Callbacks
Reliable parameterization logic for symbols and devices to improve usability and prevent invalid entries. Custom CDF callbacks for automated property validation, netlisting, and simulation integration.
Model and Corner Integration
BSIM3, BSIM4, BSIM-CMG, PSP model integration and corner mapping for schematic and simulation consistency. Support for Monte Carlo, mismatch, and process variation analysis setup.
PDK Validation and Migration
Verification of kit behavior and controlled migration support between process versions and tool environments. Automated regression testing to catch PDK issues before they impact design teams.
Expected Engagement Outcomes
- Faster onboarding into new process nodes — from weeks to days.
- Reduced PDK-related simulation and layout setup errors by up to 80%.
- More consistent design behavior across teams and projects.
- Smoother handoff between CAD and design engineering groups.
End-to-End PDK Enablement for Custom IC Teams
Setting up a Process Design Kit is one of the first and most critical steps in any custom IC design project. A misconfigured PDK can cascade into simulation inaccuracies, DRC violations, and ultimately silicon failures. SkyCadEda's PDK setup service ensures your foundry kit is correctly configured, validated, and ready for production design work.
Our team handles the complete PDK bring-up workflow: technology file creation and layer mapping, display resource configuration, design rule entry, CDF parameter setup with custom callbacks, device model integration (BSIM, PSP, EKV), process corner definition, PCell compilation and testing, and integration with your existing EDA tool environment.
Supported EDA Tools and Platforms
We work across the major custom IC design platforms: Cadence Virtuoso (IC25, Studio), Synopsys Custom Compiler, and open-source flows. Our PDK setup includes tool-specific configuration for schematic capture, layout editing, simulation environments (Spectre, HSPICE, Eldo), and physical verification flows (Calibre, Pegasus, Assura, PVS).
PDK Migration and Version Management
When foundries release PDK updates or when your organization moves to a new Virtuoso version, SkyCadEda manages the migration process. This includes techfile format conversion, CDF schema updates, PCell recompilation, SKILL compatibility testing, and regression validation to ensure nothing breaks during the transition.
Frequently Asked Questions
What is a Process Design Kit (PDK) and why is setup important?+
A PDK is a collection of files provided by a semiconductor foundry that enables chip designers to use their process technology. It includes technology files, device models, parameterized cells, design rules, and verification decks. Proper PDK setup ensures accurate simulation results, correct layout generation, and reliable physical verification — any errors in setup can cause costly tape-out failures.
Which foundry PDKs does SkyCadEda support?+
We have experience with major foundries including TSMC (180nm to 5nm), GlobalFoundries (12nm to 55nm), Samsung, UMC, and specialty fabs for RF, automotive, and mixed-signal processes. We also support IDM-internal PDKs and custom process development kits.
How long does a typical PDK setup take?+
A standard PDK setup for a single process node typically takes 1-2 weeks, including techfile configuration, CDF setup, model integration, and validation. Complex multi-mode PDKs or migration between tool versions may take 3-4 weeks.
Can you migrate PDKs between Cadence Virtuoso versions?+
Yes. We handle PDK migration between Virtuoso IC versions (IC23, IC25, Studio), including techfile format updates, CDF schema changes, PCell recompilation, and SKILL compatibility fixes.