Why Power Grid Checks Belong in Physical Verification

Physical verification is often described as DRC, LVS, and ERC, but a design that passes those three can still fail in silicon if the power distribution network cannot feed its cells. Electromigration and IR drop analysis close that gap. EM asks whether every wire and via can survive years of current stress without voiding or whisker growth. IR drop asks whether the voltage arriving at each instance is close enough to the nominal supply for the timing assumptions in the netlist to hold. Both questions are grounded in foundry reliability rules, which makes them natural members of the physical verification family rather than a separate afterthought. Treating them as core checks changes the schedule too: power grid problems discovered after routing is frozen are expensive, while the same problems found while the grid is still being shaped are usually a script change and a rerun. Teams that fold EM and IR analysis into the weekly physical verification loop tend to reach signoff with fewer emergency iterations, because the grid evolves alongside the placement and routing instead of being audited once at the end.

The Physics in One Paragraph Each

Electromigration is the transport of metal atoms caused by momentum transfer from current-carrying electrons. Over time this drifts material along a wire, eventually opening voids where atoms leave and forming hillocks where atoms pile up. The rate of damage depends strongly on current density and temperature, which is why foundry signoff rules express limits as current per wire width or per via count, often with separate limits for average, RMS, and peak current and for unidirectional versus bidirectional flow. Black's equation is the classic model linking mean time to failure to current density and temperature, and signoff tools use calibrated versions of such models to translate currents into lifetime margins. IR drop is more mundane: the power grid is a resistive network, and any current through resistance costs voltage. If a cell sees a supply rail that has sagged by a few tens of millivolts, its effective drive weakens, its timing paths slow, and any margin calculated against a nominal supply is no longer honest. Ground bounce works the same way on the return path. The two effects also interact, because elevated local temperature from a hot region accelerates EM exactly where current tends to concentrate.

Inputs: Current Maps, Technology Limits, and Temperature

Every credible EM and IR analysis stands on three inputs. The first is a current profile for the design. Static flows derive per-instance currents from library data and activity assumptions and are quick to produce, which makes them good for daily or per-revision sweeps. Dynamic flows use simulated switching activity, from vectors or from statistical activity files, to capture transient behavior and simultaneous switching. The second input is the technology rule deck: foundry-supplied EM limits per layer and per via class, voltage-dependent constraints where applicable, and the design rules the grid must respect. The third is temperature. EM accelerates with heat, and resistance rises with temperature, so an honest analysis needs either a thermal map from a power-aware run or a documented worst-case assumption. Getting these inputs wrong does not just reduce accuracy, it changes decisions: an optimistic activity file can hide a real EM risk on a clock strap, and a pessimistic uniform temperature can flood the team with violations that never matter. Documenting which activity source and which temperature scenario a given run used is as important as the results themselves, because signoff review will ask.

Static IR Drop: Reading the Voltage Map

A static IR run solves the resistive power network with average currents and reports the voltage at every instance. The result is usually presented as a heat map over the floorplan, and the first reading skill is resisting the urge to chase the single worst spot. Systematic patterns matter more than isolated minima. A gradient that worsens toward one corner suggests the pad ring or bump assignment is unbalanced. Deep drops in narrow bands often trace to a missing strap tier above a dense macro row. Uniform mild drop everywhere points to global resistance, perhaps too few metal layers committed to power. A useful habit is to compare the worst drop against the budget agreed with timing, not against zero: the signoff question is whether timing closure assumptions remain valid at the worst-case delivered voltage. It also pays to check symmetry. Blocks with identical placement density should show similar maps, and divergence between them usually means one of them lost vias or straps during an ECO. Static analysis is cheap enough to run on every significant grid change, and treating it as a regression check, with a recorded worst-drop number per revision, catches slow degradation that a one-time audit never will.

Dynamic IR and the Role of Decoupling Capacitance

Static maps hide the problems that come from switching. When many gates flip in the same cycle, the instantaneous demand can far exceed the average, and the local supply dips until charge arrives from decoupling capacitance and the grid. Dynamic IR analysis applies time-based current waveforms and reports the worst transient droop per instance and per clock cycle. The classic findings are clusters near clock trees and wide datapaths at activity boundaries, plus false-looking hotspots where an overly correlated activity file models impossible simultaneity. Decoupling capacitance is the main lever: well-placed decap near hungry switching regions supplies charge locally, flattening the droop. But decap is not free. It leaks, it costs area, and blanket sprinkling wastes both, so the productive flow is to look at the droop map, add decap where the violations actually are, and re-run. Another lever is scheduling: spreading switching across cycles through useful skew or clock gating reduces peak demand without touching the grid at all. Dynamic analysis is also where package and board effects start to matter, since the die grid is only as stiff as the supply feeding it, so serious flows model the package network together with the on-chip grid rather than assuming an ideal source.

EM Signoff: Current Density, Vias, and Hotspots

EM signoff walks every segment and via in the power and signal networks and compares carried current against the technology limit for that geometry and layer. The engineering work is mostly in the exceptions. A violation on a wide clock strap deserves a different response than one on a short signal jumper, and the tool cannot know which nets the team considers critical, so an EM review that starts by classifying nets by importance saves days. Common root causes repeat across projects. Vias single-cut by default in older flows fail arrays elsewhere in the industry for years. Wires narrowed by a via resize or a last-minute ECO quietly drop below their limit. Macros with enormous aggregate current sit on grids designed before the macro choice was made. The fixes are correspondingly local: widen the segment one routing track, double the via array, split the current path, or add a strap. What must be resisted is waiving by proximity, where a reviewer clears violations in a region because the block historically passed. Each waiver should name the reason, the current value, the limit, and the expected lifetime context, exactly as with DRC waivers, because EM failures surface months or years later and the waiver record is the only traceability anyone will have.

Flow Integration and Incremental Checking

The most reliable way to keep EM and IR analysis from becoming a signoff-week crisis is to run it incrementally. A practical flow attaches IR and EM checks to the existing physical verification cadence: full-chip static runs on every grid or floorplan change, dynamic runs at fixed milestones when activity data is trustworthy, and EM sweeps after each major route revision. Results should land in the same review channel as DRC and LVS metrics, with a small set of tracked numbers, worst static drop, worst dynamic droop, worst EM margin, and violation counts by severity, so a regression is visible at a glance. Automation matters here. A scripted run with fixed inputs and a stable report format turns power integrity into a gate the whole team can see, instead of expert tribal knowledge invoked late. The same scripts that wire EM and IR checks into the loop also make recovery cheap when a failure does appear, because the input snapshot and report from the failing revision identify exactly which change introduced the problem. Teams that reach tapeout calmly on power integrity are rarely the ones with the cleverest final-week analysis; they are the ones whose grid was measured continuously while there was still time to respond.